1. Field of the Invention
The present invention relates to a method of designing integrated circuits (ICs) and more particularly, to a method of designing the layout for ICs using a Computer-Aided Designing (CAD) system or tool, which makes it possible to route the signal lines without their re-routing process.
2. Description of the Related Art
Conventionally, well-known Application Specific Integrated Circuits (ASICs) termed Gate Arrays, Standard Cells, and so on have been designed using a CAD tool, in which the Clock Tree Synthesis (CTS) process has become to play an important role. The CTS process is a process to control the propagation delay of a clock signal by assigning a clock driver (i.e., buffer) to each cell array to thereby adjust the delay with the extra capacitance and resistance added by the driver.
With the CTS process, the clock lines for the respective blocks or cells are synthesized in the form of a tree and then, buffers having high driving capability are assigned to the respective branches of the clock line tree. Thus, the relative skew (i.e., the phase difference) of the propagated clock signal among the blocks and/or cells are suppressed, in other words, the clock skew is reduced.
The CTS process is well known and therefore, no further explanation will be needed. However, an example of the documents explaining this process is as follows:
The user""s manual (provisional) of the CAD tool, CB-C9 family, VX/VM type, for 0.35 xcexctm CMOS cell-based ICs, Design section, published by NEC corporation in 1997.
An example of a prior-art method of designing the layout for ICs using a CAD tool will be explained below with reference to FIGS. 1 to 6.
FIG. 1 shows the layout section of a CAD tool for conducting the prior-art method. The layout section of FIG. 1 comprises a cell information library 101, a timing restriction information storage 102, a placement and routing information storage 103, a functional block placement section 104, a power and ground line routing section 105, a cell placement section 106, a clock line routing section 107, a signal line routing section 108, and a clock and signal line re-routing section 109.
The cell information library 101 stores the cell information for defining the primitive cells. Each of the primitive cells has one of the minimum functions (e.g., a NAND or NOR circuit, an inverter, a buffer, and a flip-flop) that have been prepared to design cell-based ICs. Also, the library 101 stores the wiring layer information for defining the extending direction of the respective wiring layers in the primitive cells.
The cell information in the library 101 is read out and sent to the functional block placement section 104 and the cell placement section 106 as necessary. Also, the cell information and the wiring layer information in the library 101 is read out and sent to the power and ground line routing section 105, the clock line routing section 107, the signal line routing section 108, and the clock and signal line re-routing section 109 as necessary.
The timing restriction information storage 102 stores the timing restriction information about the temporal restriction in signal transmission among the logic elements (i.e., about the timing restriction of the signals other than the clock signal). The timing restriction information in the storage 102 is read out and sent to the cell placement section 106 and the signal line routing section 108 as necessary.
The placement and routing information storage 103 stores the placement information of the primitive cells in the form of net list and the routing information of the wiring lines among the primitive cells. The placement information and the routing information is read out and sent to the functional block placement section 104, the power and ground line routing section 105, the cell placement section 106, the clock line routing section 107, the signal line routing section 108, and the clock and signal line re-routing section 109 as necessary.
The functional block placement section 104 determines the functional blocks (i.e., the areas where the primitive cells are functionally separated and laid out), forming a floor plan. This operation is performed on the basis of the cell information from the library 101 and the placement and routing information from the storage 103. Then, the section 104 supplies the result of the placement (i.e., the floor plan) to the power and ground line routing section 105.
The power and ground line routing section 105 conducts the routing operation of the power supply lines and the ground lines on the basis of the cell information from the library 101 and the routing information of the wiring layers from the storage 103. Then, the section 105 supplies the result of the routing operation to the cell placement section 106.
The cell placement section 106 determines the layout of the primitive cells for each functional block on the basis of the cell information from the library 101, the placement and routing information from the storage 103, and the timing restriction information from the storage 102. Then, the section 106 supplies the result of the layout operation to the clock line routing section 107.
The clock line routing section 107 conducts the CTS process on the basis of the cell information from the library 101 and the placement and routing information from the storage 103, thereby determining the routing of the clock lines for each primitive cell. Then, the section 107 supplies the result of the clock line routing operation to the signal line routing section 108.
The signal line routing section 108 conducts the routing operation of the signal lines for each primitive cell on the basis of the cell information from the library 101, the placement and routing information from the storage 103, and the timing restriction information from the storage 102. Then, the section 108 supplies the result of the signal line routing operation to the clock and signal line re-routing section 109.
The clock and signal line re-routing section 109 searches the result of the signal line routing operation thus sent and extracts the short-circuited ones therefrom. Then, the section 109 conducts the re-routing operation (i.e., amends the existing layout) of the short-circuited signal lines and the relating clock lines to eliminate the short-circuited ones on the basis of the cell information from the library 101, the placement and routing information from the storage 103, and the timing restriction information from the storage 102. Thus, the section 109 generates the final result of the layout operation and outputs it as the final layout information.
FIG. 2 shows a prior-art layout method conducted with the layout system shown in FIG. 1.
First, in the step S101, the functional block placement section 104 places the functional blocks including the primitive cells to form a floor plan on the basis of the cell information from the library 101 and the placement and routing information from the storage 103.
In the next step S102, the power and ground line routing section 105 determines the routes of the power lines and the ground lines on the basis of the cell information and the wiring layer information from the library 101.
In the next step S103, the cell placement section 106 places the primitive cells in each of the functional blocks on the basis of the cell information from the library 101, the placement and routing information from the storage 103, and the timing restriction information from the storage 102. In this process, the primitive cells are laid out at the specific positions where the timing of the ordinary signals other than the clock signal is judged optimum. If the timing restriction information is not satisfied after a layout of the primitive cells is completed, this layout is amended. This amendment process of the layout is repeated until the restriction information is satisfied.
FIG. 3 shows an example of a primitive cell defined by the cell information from the storage 101. The primitive cell 124 in FIG. 3 has connectable terminals 113, 114, 115-1, and 115-2 to which the wiring lines in the (nxe2x88x921) th wiring layer are connectable, where n is a natural number greater than unity. The cell 124 has prohibited areas 116 also. The wiring lines in the (nxe2x88x921)-th wiring layer are prohibited from overlapping with the areas 116.
In the step S103, the primitive cell 124 and/or any other primitive cell (not shown) is assigned to each of the functional blocks where the routes of the power and ground lines has been determined in the step S102.
In the next step S104, the clock line routing section 107 conducts the CTS process on the basis of the cell information from the library 101 and the placement and routing information from the storage 103, determining the routes of the clock lines for each primitive cell. Specifically, the section 107 determines the routes of the clock lines so as to amend the dispersion or fluctuation of the propagation delay of the same clock signal in the respective branched clock lines. Through this CTS process, the clock lines are laid out in such a way that the relative skew of the clock signal is minimized in the whole IC.
FIG. 4 shows the result of the above-described steps S101 to S104 in the primitive cell 124 of FIG. 3. As seen from FIG. 4, a power supply line 118 and a ground line 119 in the (nxe2x88x921)th wiring layer are respectively laid out at the top and bottom of the cell 124 horizontally (i.e., in the X direction). A power supply line 120 in the n-th wiring layer, which is connected to the underlying power line 118 by way of a through hole 117, is laid out vertically (i.e., in the Y direction) to overlap with one of the underlying prohibited areas 116. A clock line 122 in the n-th wiring layer is laid out vertically to overlap with the connectable terminal 114 and two of the underlying prohibited areas 116. The clock line 122 is adjacent and parallel to the power line 120.
Although the power line 120 and the clock line 122 are overlapped with one of the prohibited areas 116 and at the same time, the clock line 122 is overlapped with the terminal 114 and the two of the areas 122, no problem occurs. This is because the lines 120 and 122 are located in the n-th wiring layer while the areas 116 prohibits the overlapping in the (nxe2x88x921)-th wiring layer and the terminal 114 is connectable to the wiring lines in the (nxe2x88x921)-th wiring layer.
In the next step S105, the signal line routing section 108 determines the routes of the signal lines for each of the primitive cells on the basis of the cell information from the library 101, the placement and routing information from the storage 103, and the timing restriction information from the storage 102.
In the primitive cell shown in FIG. 3, a signal line (not shown) to be connected to the terminal 114 in the n-th wiring layer is unable to be connected to the terminal 114. This is because the clock line 122 has been placed to overlap with the terminal 114 in the n-th wiring layer after the step S104, as shown in FIG. 4. Therefore, in the step S105, as shown in FIG. 5, a horizontal signal line 125 extending in the X direction is placed in the (nxe2x88x921)-th wiring layer. In this case, however, the signal line 125 overlaps with one of the prohibited areas 116 in the (nxe2x88x921)-th wiring layer located in the circle 126, resulting in unwanted short-circuit of the signal line 125.
Accordingly, in the next step S106, the clock and signal line re-routing section 109 extracts the signal lines thus short-circuited on the basis of the routing result of the signal lines outputted from the signal line routing section 108.
In the next step S107, the clock and signal line re-routing section 109 performs the re-routing operation of the short-circuited signal lines thus extracted and their relating clock lines on the basis of the cell information from the library 101, the placement and routing information from the storage 103, and the timing restriction information from the storage 102.
In the primitive cell 124 shown in FIG. 3, after the step S107, as shown in FIG. 6, the vertical clock line 122 placed in the n-th wiring layer to overlap with the underlying terminal 114 (see FIG. 5) is shifted toward the right-hand side (i.e., toward the +X direction) in the same n-th wiring layer until the line 122 overlaps with the underlying terminal 115-1. At the same time, a vertical signal line 121 is additionally provided in the (nxe2x88x921)-th wiring layer between the power line 120 and the clock line 122. Thus, the signal line 121 thus added is connected to the terminal 114 at its end in the (nxe2x88x921)-th wiring layer. A signal line such as the line 121 with its end on a terminal is termed a xe2x80x9ccushionxe2x80x9d.
For example, for a cell-based IC having approximately 790xc3x97103 transistors and approximately 58xc3x97103 cells, the re-routing operation as described here needs to be conducted at approximately 2000 positions.
Alternately, if the horizontal short-circuited signal line 125, which overlaps with one of the prohibited areas 116 as shown in the circle 126 of FIG. 5, is not re-routed in the step S107, there is a possibility that the terminal 114 is kept unconnected or unwired.
As explained above, with the prior-art layout method as shown in FIG. 2, there is a problem that short-circuit of the signal lines tends to occur and as a result, the re-routing operation of the clock lines is essentially required to eliminate the short-circuited signal lines.
Moreover, because of the re-routing operation of the clock lines, the relative skew of the clock signal that has been adjusted to be minimized or optimized through the CTS process is changed, resulting in another problem that the relative skew of the clock signal deteriorates.
Unless the re-routing operation is not conducted, there is a further problem that short-circuited signal lines and unconnected terminals may be left.
Accordingly, an object of the present invention is to provide a method of designing the layout for an IC that eliminates the necessity of the above-described re-routing operation of the signal lines.
Another object of the present invention is to provide a method of designing the layout for an IC that makes it possible to optimize or minimize the relative skew of the clock signal.
Still another object of the present invention is to provide a method of designing the layout for an IC that eliminates short-circuited signal lines and unconnected terminals.
The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description.
According to a first aspect of the present invention, a method of designing layout for an IC using a CAD system is provided. This method comprises the steps of:
(a) defining prohibited areas in each of stacked wiring layers;
the prohibited areas causing an obstacle to define layout of signal lines in each of the wiring layers if a clock line is defined to intersect at least one of the prohibited areas;
(b) defining layout of clock lines in each of wiring layers through a clock tree synthesis process in such a way that none of the clock lines intersects the prohibited areas; and
(c) defining layout of signal lines in each of the wiring layers after the step (b).
With the method of designing layout for an IC according to the first aspect of the invention, the prohibited areas are defined in each of stacked wiring layers in the step (a), where the prohibited areas are areas that cause an obstacle to define the layout of the signal lines in each of the wiring layers if a clock line is defined to intersect at least one of the prohibited areas. Then, in the step (b), the layout of the clock lines is defined in each of the wiring layers through a clock tree synthesis process in such a way that none of the clock lines intersects the prohibited areas. Thereafter, in the step (c), the layout of signal lines is defined in each of the wiring layers. Accordingly, there is no possibility that some of the signal lines is/are shifted (i.e., the layout of the signal lines is partially redefined) in the step (c) due to existence of the clock line or lines that has/have been already defined.
As a result, the re-routing operation of the signal lines required in the above-described prior-art method can be eliminated. This will eliminate short-circuited signal lines and unconnected terminals.
Moreover, since there is no possibility to redefine the optimized layout of the clock lines, the relative skew of the clock signal is optimized or minimized.
In a preferred embodiment of the method according to the first aspect, each of the prohibited areas includes a terminal to which one of the signal lines is to be connected.
In another preferred embodiment of the method according to the first aspect, a step of providing prohibited area information about a primitive cell including at least one of the prohibited areas is additionally provided. Then, the prohibited area information is used in the clock tree synthesis process in the step (b).
In still another preferred embodiment of the method according to the first aspect, a step of providing prohibited terminal information about terminals corresponding to the prohibited areas is additionally provided. Then, the prohibited terminal information is used in the clock tree synthesis process in the step (b).
In a further preferred embodiment of the method according to the first aspect, the clock lines and the signal lines are located in a same one of the wiring layers. In this embodiment, it is preferred that the clock lines and the signal lines extend in a same direction.
According to a second aspect of the present invention, another method of designing layout for an IC using a CAD system is provided. This method comprises the steps of:
(a) providing prohibited area information about primitive cells including at least one of prohibited areas;
the prohibited areas causing an obstacle to define layout of signal lines if clock lines are defined to intersect the prohibited areas;
(b) providing cell information about primitive cells excluding the prohibited areas;
(c) placing functional blocks using the cell information;
(d) routing power lines and ground lines using the cell information;
(e) placing primitive cells using the cell information;
(f) routing clock lines through a clock tree synthesis process using the prohibited area information; and
(g) routing signal lines using the cell information.
With the method of designing layout for an IC according to the second aspect of the invention, the prohibited area information about primitive cells including at least one of prohibited areas is provided in the step (a) and the cell information about primitive cells excluding the prohibited areas is provided in the step (b). The prohibited areas cause an obstacle to define layout of signal lines if clock lines are defined to intersect the prohibited areas.
Furthermore, the functional blocks are placed using the cell information in the step (c), the power lines and ground lines are routed using the cell information in the step (d); the primitive cells are placed using the cell information in the step (e); the clock lines are routed in the step (f) through a clock tree synthesis process using the prohibited area information, and the signal lines are routed in the step (g) using the cell information.
Accordingly, the re-routing process of the signal lines required in the above-described prior-art method can be eliminated. This will prevent short-circuit of the signal lines and occurrence of the unconnected terminals. Also, since there is no possibility to redefine the optimized layout of the clock signals, the relative skew of the clock signal is optimized.
In a preferred embodiment of the method according to the second aspect, placement information about the primitive cells and routing information about wiring lines (i.e., the signal lines and the clock lines) among the primitive cells is used in each of the steps (c) to (g). Timing restriction information is additionally used in each of the steps (e) and (f).
According to a third aspect of the present invention, still another method of designing layout for an IC using a CAD system is provided. This method comprises the steps of:
(a) providing prohibited terminal information about primitive cells including at least one of prohibited terminals;
the prohibited terminals causing an obstacle to define layout of signal lines if clock lines are defined to intersect the prohibited terminals;
(b) providing cell information about primitive cells excluding the prohibited terminals;
(c) placing functional blocks using the cell information;
(d) routing power lines and ground lines using the cell information;
(e) placing primitive cells using the cell information;
(f) routing clock lines through a clock tree synthesis process using the prohibited terminal information; and
(g) routing signal lines using the cell information.
With the method of designing layout for an IC according to the third aspect of the invention, the same process steps are carried out, except that the prohibited terminal information is used instead of the prohibited area information in the method according to the second aspect. Therefore, the same advantage as those in the method of the second aspect are given.
In a preferred embodiment of the method according to the third aspect, placement information about the primitive cells and routing information about wiring lines (i.e., the signal lines and the clock lines) among the primitive cells is used in each of the steps (c) to (g). Timing restriction information is additionally used in each of the steps (e) and (f).